FPGA's What are they and should I use one in my robot?

 

FPGA’s

 

 

What are they and should I use one in my robot?

 

Field Programmable Gate Array’s or FPGA’s are very powerful devices that in certain circumstances can greatly outperform traditional Central Processing Unit’s (CPU) running at 20 times the clock speed.

FPGA’s are however very different to CPU’s in as much as CPU’s run programs and FPGA’s are arrays of logic gates who’s function and connections are designed.  Their power comes from the fact they run all the gates at the same time, where as CPU’s execute the program instructions one at a time.  In fact you can even design a CPU to be implemented in an FPGA that will run at the clock speed of the oscillator you feed into the FPGA.  For that mater you  could re-create the CPU from an Arduino Uno in an FPGA and run it at 50 MHz, way faster than the 16 MHz we are all familiar with. If you try to simulate an FPGA with a CPU, you will find the simulation will run far slower than the real FPGA.

So if FPGA’s are so powerful, why not just ditch the CPU’s and use FPGA’s instead.

Simple, FPGA’s are so much  more expensive compared to CPU’s.

In fact companies such as  ARM use FPGA’s to test their latest CPU design in FPGA’s to make sure they work.  In this role, FPGA’s are used to test Application Specific Integrated Circuit (ASIC) designs before they go to manufacture.

The only  time you would use an  FPGA in a production board, is if it was a limited run, tooling up a chip fabrication plant to produce an ASIC can be very costly and not viable unless you are producing many thousands of the chip.

As for should we use FPGA’s in our robots, it’s really comes down to the application.

FPGA’s are good  for protocol translation or for simple control systems, I doubt you would ever replace a CPU in a computer with an FPGA,  but you would use an FPGA to help support the CPU.

 

In the following description on how to configure an FPGA, I will be using a cheap Altera Cyclone II with the EP2C5T144 FPGA chip with a EPCS4 EEPROM, 50 MHz Crystal Oscillator, 3 LED and a push button.

 I was able to purchase the above FPGA development board with a USB Blaster programming device for  around AU$25

 

To configure the above FPGA, you will need to sign up with Intel (They purchased Altera) as a maker/student and download the Quartus II 13.1SP1 Web edition of the IDE.  This version is free to down load and use with restrictions, such as only using a single tread when synthesizing your designs.  You can purchase a licence to fully enable the IDE and unlock a few other tools, if you have a spare  US$4000 per year. but for what we will be doing you won’t need it.

There are new version of Quartus II available, but they don’t support the Cyclone II FPGA used on the board above.

Quartus II supports VHDL, Verilog and SystemVerilog, In the examples below I will be using Verilog.  I chose this language because I could.

 

Verilog at first glance looks like a programming language, but don’t get caught out, designing in Verilog and programming are very different. 

Here is a sample of code from Verilog.

 

module BaseModule (i_POR, i_Clk, i_Button, o_LED);

 

input      wire     i_POR;                // Power On Reset              Pin 73

input      wire     i_Clk;                // 50MHz Crystal Clock         Pin 17

input      wire     i_Button;             // Push Button                 Pin 144

output     reg    [2:0] o_LED;            // LED0-2                      Pin 3, 7, 9

 

integer    count;  // By defualt integers in Verilog are 32 bit, this one is used as a counter

reg        [2:0]  LED;  // This is used as a binary counter for the LED output.

 

always @(posedge i_Clk) begin // we want this to be run only on the positive edge of the Xtal ocilator

     if (!i_POR | !i_Button) begin                // If the Power On Reset or the Button are active, reset all out variables

        count = 0;

        o_LED = 3'b000;

        LED = 3'b000;

     end else begin

        count = count + 1;  // increment the count on each posedge of the clock signal

        if (count > 25000000) begin   // the clock runs at 50MHz, so if we count 25,000,000 counts, thats one second.

          count = 0;     // reset the count back to 0 ready for the next cycle.

          LED = LED + 3'b001;     // increment the LED by one, when the LED is at 111 and we add 1 it will overflow back to 000.

        end

      end

      o_LED[0] = !LED[0];    // our LED outputs are inverted, 

      o_LED[1] = !LED[1];    // so we need to invert each bit of 

      o_LED[2] = !LED[2];    // our LED count to the LED's

    end

 

endmodule

 

 

At first glance, this looks like standard programming code, This code is sort of like the Hello World type file for FPGA’s

The first line is the module declaration using the keyword module. Note all keywords in Verilog are lower case and are case sensitive.  The next word is the name of the module, then in brackets are the IO definitions.  In FPGA’s that are always inputs and outputs and sometimes the IO definition is for both and input and an output that is tri-state.  If you look at the end of the code section, you will find an endmodule statement, You can define multiple modules withing a single  file, but this is not commonly done, its easier to  debug  your design when the modules are in separate files.

 

The next for lines of code define what the IO is, An input, output or inout. In our example I’m not going to cover the inout, its a lot more complicated to drive.

 

At this point you may have noticed that I have defined a Power On Reset and a 50 MHz Clock as inputs.  This is not a mistake.  The FPGA it’s self doesn’t need a clock, but I will need them for what I’m doing.  

The Input statement is followed by a structural type, basically you will use either wire or reg, for an input, it will be a wire, then we have the input name.

The output statement can be either a reg or a wire, however you can  only use a wire if your code is continuously driving the output.  In our case we won’t be so need to use the reg keyword.  The next bit is [2:0].  This defines the number of bits used in this output, in this case 3 bits Most Significant Bit (MSB) first. then finally the output name.

 

Next I need a couple of registers for holding data, In this version  of Verilog an integer is 32  bits signed.

With the keyword reg, we are defining a register, by default this will be a single bit unless we specify other wise, in this case I have with the [2:0] defined a  3 bit register.

 

The next major section is the always loop.

in this case 

always @(posedge i_Clk) begin

In this case when ever the i_Clk input transitions from low to high, the code block between the begin and the matching end statements will be operated. 

 

next we have the following:

if (!i_POR | !i_Button) begin

The  | is the or specifier.

The ! mark is a not specifier.

This if statement will operate the block of code between the following begin and end statements when the i_POR is not on or the i_Button is not on.

I should mention at this point, on this dev board, when power is applied, the i_POR input is held low for a short time while the board is powered up. and the button will pull the input low when pushed. Another thing to keep in mind, when we are doing  our pin assignment later on, we also need to make sure the input is pulled high by the internal pull up resistors. Pin assignment are not done in our Verilog code, but as a separate setting in Quartus II

Basically, I wan’t this next section of code to be operated when the circuit is powering up or when the button is pressed, I’m using the button here as a reset button.

 

        count = 0;

        o_LED = 3'b000;

        LED = 3'b000;

The above section of code  is what is being operated whenever the reset is being run.

The count = 0; should be self explanatory.

the o_LED = 3’b000; needs a bit more explaining.

Here we have a 3 bit variable.  If we assigned 0; to it, then Quartus II will synthesize it, but it will also report warning about truncating the value  we are assigning to our register.

To get around this I have fully specified the value to store in the register, the 3 is the number of bits, the ’b indicates a binary value and the 000; are each of the bits.

Setting the o_LED to 3'b000; will in this dev board turn on all the LED’s

 

the else statement is supported

end else begin

 

ok so this next block of code is only going to operate on the rising edge of the i_Clk when the button is not pushed and the POR is not active.

count = count + 1;

if (count > 25000000) begin

  count = 0;

  LED = LED + 3'b001;

end

I think this is pretty simple, each clock pulse will increment the counter, at 25,000,000 counts, the block after the if statement is operated, that resets the counter and increments our internal LED counter.

After that we have the end statement that matches up with out POR/reset if block, but we are still in the always block.

o_LED[0] = !LED[0];

o_LED[1] = !LED[1];

o_LED[2] = !LED[2];

Ok, this is why we had to use an internal counter, the outputs need to be inverted, and that what the above block does.

 

So we now have our module defined. 

Next we need to compile it.

The above bit of code will use 88 logic element in our FPGA, we have 4,608 logic elements to play with on our FPGA on the dev board.

It will then create a circuit that looks like this

 

Some YouTube videos will tell  you that a lot of warnings are created and that you can ignore them,  I’m telling you don’t, find out what they are first, some warning can be ignored, but not all.

For example:

Warning (20028): Parallel compilation is not licensed and has been disabled

can be safely ignored, but a warning on data truncation could be a warning you have a bug in your code causing it not to work as intended.

 

OK, so the above design can be done with an Arduino Nano costing less than AU$5, why would you use an FPGA?

Yes it can, this was after all only the Hello world example.

 

The real power in the FPGA is in its ability to perform operations in parallel.

You could for example create a FIFO block that is 128 bits wide and 1024 registers deep, and it will clock in all 128 bit and ripple the data through the entire 1024 register in one clock cycle.

You can use it to create a display driver, generating HDMI signals for a monitor and all multiplex externally connected ram with input from a CPU.

This is just a basic introduction to the FPGA. 

For more information on how to use Verilog check out http://www.asic-world.com/verilog/veritut.html

 


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GroG's picture

Thanks Ray. Nice overview. 

Thanks Ray.
Nice overview.  So, with the student license you get a working parallel board - or is it really disabled as the warning says.  Did the Web-IDE generate the picture ?   Is it capable of drag/drop elements like eagle-cad ?

Ray.Edgley's picture

Hello Grog, It's only the

Hello Grog,

It's only the compiling on the computer that disabled.
 

By it's very nature, every gate on the FPGA is actually running in parallel.

So on the FPGA pictured there are 4,608 logic units each working in parallel.

This where it's harder for a programmer to get their minds around, with FPGA you are designing a circuit, the HDL is a text way of describing the circuit.

This gets to be confusing when you find the for statement as an example.
It's syntax is very much like C or Java, but its operation is very different.

In a sequential language like C or Java, the results of a for loop can be used in the input of the next loop in the same for loop.   This is not the case with FPGA's
Each loop in the for statement is describing another copy of the same circuit that is running at the same time, so the results of one for loop are not yet available for the next loop.

The other thing to catch out the unwary, the speed of the FPGA is not governed by the included 50 MHz crystal oscillator, It is governed by the propagation delays in the transistors in the FPGA,in the case of the one used above that around 336 MHz

If you look at the design of a Apple MacBook from say  5 years ago,  the largest chip on the board is an FPGA.
The model number escapes me at this time, but in that MacBook, they included an Intel CPU with integrated VPU and an  NVIDIA GPU, they used the FPGA to select which video output would be sent to the screen.

Yes the web IDE did generate the image.
The definition of WebIDE is not what I would have called a web interface. (not  sure why they call it a web version)

You  download the Web edition and install it, it runs like any other IDE on the computer, and does not use outside hardware, it will with when the internet is down.

The other little gotcha, is you need an IDE installed for each brand of FPGA you want to program.
Some of the more common ones are the Intel Altera chips, the Xilinx and the Latice.
There are others but not as well known.

 

Ray